1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and in particular to an improved semiconductor device and a fabrication method thereof by which it is possible to fabricate a dome-shaped semiconductor device.
2. Description of the Conventional Art
As a semiconductor device for increasing the integrity and electrostatic capacitance thereof, a pillar type capacitor of a conventional semiconductor device as shown in FIG. 1 and a fin type capacitor as shown in FIG. 3 have been used.
The conventional semiconductor device having a pillar type capacitor and a fabrication method thereof will now be explained.
First, FIG. 1 illustrates a conventional semiconductor device having a conventional pillar type capacitor. As shown therein, on a semiconductor substrate 1, a word line 2 is formed. Dopant regions 19a and 19b are formed in the semiconductor substrate 1 at both sides of the word line 2. The word line 2 acts as a gate electrode, and the dopant regions 19a and 19b act as a source electrode and a drain electrode, respectively. A silicon oxide film 3 which acts as an insulation film, is formed on the upper surface of the semiconductor substrate 1, and a silicon nitride film 4 is formed on the upper surface of the silicon film 3. A contact hole 19 is formed to pass through the silicon oxide film 3 and the silicon insulation film 4, respectively, and communicates with the drain electrode 19b. A polysilicon film 11 is formed within the contact hole 18 and on the upper surface of the silicon nitride film 4. At this time, the polysilicon film 11 acts as a node electrode 14 of the capacitor. An insulation film 12 which acts as a dielectric, is formed on the 5 polysilicon film 11 and the silicon nitride film 14. A conductive polysilicon film 13 is formed on the surface of the insulation film 12. The polysilicon film 13 becomes a plate electrode 13 of the capacitor. An insulation film 17 having a flat surface is formed on the upper surface of the plate electrode 13. A contact hole is formed in a portion of the source electrode 19a. A bit line 14 of a polysilicon layer which is a conductive layer, is formed on the upper surface of the insulation film 17 and on an inner surface of the contact hole is formed and is connected with the source electrode 19a.
The fabrication method of a semiconductor device having a pillar type capacitor will now be explained with reference to FIGS. 2A through 2H.
First, as shown in FIG. 2A, a gate electrode 2 made of a polysilicon is formed on the upper surface of the p-type semiconductor substrate 1, and an n-type dopant ion is implanted into the semiconductor substrate at both sides of the gate electrode 2 by a self-align method for thus forming the source electrode 19a and the drain electrode 19b, and then a multiple layer film 20 is formed on the upper surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method in such a manner that the gate electrode 2, the source electrode 19a, and the drain electrode 19b are surrounded thereby. The multiple insulation film 20 is formed by sequentially depositing a silicon oxide film 3, a silicon nitride film 4, and a silicon oxide film 5 on the upper surface of the semiconductor substrate. The silicon nitride film 4 is used as an etching finishing film.
Next, as shown in FIG. 2B, a contact hole 18 is formed by selectively and anisotropically etching the multiple insulation film 20 formed on the drain electrode 19b. A polysilicon layer is deposited on an inner surface of the contact hole 18 and the upper surface of the multiple insulation film 20. The first conductive layer 6 is used as a node electrode of the capacitor. A n-type dopant may be added to the first conductive layer 6 for increasing a conductivity of the first conductive layer 6. In the method for adding the n-type dopant, the n-type dopant is mixed with a deposition gas for forming the first conductive layer 6, so that the n-type dopant is added to the first conductive layer 6 at the time of depositing the conductive layer 6. In another method for adding the same, the first conductive layer 6 formed of a non-doped polysilicon layer is formed by the CVD (Chemical Vapor Deposition) method, and then the n-type dopant ion may be implanted by an ion implantation method. The first conductive layer 6 may be formed of a polysilicon layer, or the first conductive layer 6 may be formed of a high temperature melting metal or a silicide film formed of a high temperature melting metal.
Next, as shown in FIG. 2C, on the upper surface of the first conductive layer 6, a multiple insulation film 30 formed of a first silicon oxide film (non-doped silicate glass: hereinafter called a first NSG) 7, a P.sub.2 O.sub.5 -doped silicon oxide film (phosphor silicate glass: hereinafter called a PSG) 8, and a second non-doped silicon oxide film (non-doped silicate glass: hereinafter called a second NSG) 9 is formed. Thereafter, the multiple insulation film 30 is annealed at a temperature of about 900.degree. C. for about 20 minutes. The etching speeds of the first NSG 7, the PSG 8 and the second NSG 9 of the multiple insulation film 30 are different at the time of wet-etching, compared to the state that the annealing is not performed. An etching mask (not shown) is formed on the second NSG 9, and the multiple insulation film 70 is anisotropically etched by using the etching mask for thus forming a pattern having a vertical lateral surface on the first conductive layer 6 on the contact hole 18. When etching the resultant structure by a reactive ion etching method by using the photoresist film as an etching mask, and a chloro fluoro carbon as an etching gas, since there is an etching speed difference between the second NSG 9, the PSG 8, and the first NSG 7, it is possible to obtain a desired pattern having a vertical lateral surface.
Next, as shown in FIG. 2D, the multiple insulation film 30 formed of the second NSG 9, the PSG 8 and the first NSG 7 is wet-etched for about 2 minutes by using a 20:1 solution of NH.sub.3 :HF. At this time, when wet-etching the resultant structure by using the 20:1 solution of NH.sub.3 :HF, since the PSG 8 having a high density dopant has a high etching speed compared to the first NSG 7 and the second NSG 9, it is possible to obtain a pattern having a recessed etching lateral surface of the PSG 8 as shown in FIG. 2D.
Next, the second conductive layer 10 formed of a polysilicon layer having an n-type dopant as shown in FIG. 2E is formed on the upper surface of the first conductive layer 6 in such a manner that the second conductive layer 10 fully covers the NSG 9, the PSG 8 and the first NSG 7. Preferably, the second conductive layer is formed of a polysilicon layer having a dopant in order to reduce the resistance. The semiconductor substrate 1 is inserted into a chemical vapor deposition reactor, and the second conductive layer 10 is deposited in a state that the temperature of the chemical vapor deposition reactor is increased to a temperature of above 450.degree. C. in order to prevent the resistance from being increased as the insulation film is formed due to a natural oxide film formed on a boundary surface between the first conductive layer 6 and the second conductive layer 10.
The second conductive layer 10, as shown in FIG. 2E, is etched back by an anisotropical etching process until the second NSG 9 is exposed, so that the second conductive layer 10 remains on only the lateral surfaces of the second NSG 9, the PSG 8, and the first NSG 7 as shown in FIG. 2F.
As shown in FIG. 2G, the second NSG 9, the PSG 8, and the first NSG 7 are etched by using a hydrogen fluoride solution, and then the node electrode 11 of the capacitor is formed. At this time, the silicon oxide film 5 is also etched. In addition, since the silicon nitride film 4 is not etched with respect to the hydrogen fluoride solution, the silicon nitride film 4 is used as an etching finishing film.
An insulation film 12 which is a dielectric, is formed on the upper surface of the silicon nitride film 4 and the surface of the node electrode 11, and a conductive layer 13 is formed on the upper surface of the insulation film 12, as illustrated in FIG. 2H. The thusly formed insulation film 12 becomes a dielectric film of a capacitor, and the conductive layer 13 becomes a plate electrode 13 of the capacitor. An insulation film 17 is formed on the upper surface of the plate electrode 13, and then the semiconductor substrate 1 is flattened. The insulation film 17, the insulation film 12, the silicon nitride film 4, and the silicon oxide film 3 which are formed on the source electrode 19a, are etched for thus forming a contact hole. Thereafter, the polysilicon is deposited on the contact hole and then is patterned for thus forming a bit line 14 connected with the source electrode 19a and finishing the fabrication of a semiconductor memory device having a pillar type capacitor.
FIG. 3 illustrates a conventional semiconductor device having a fin type capacitor. As shown therein, a word line (not shown) is formed on the semiconductor substrate 1, and a gate electrode 2 connected with the word line 2 is formed therein. Dopant regions 19a and 19b are formed within the semiconductor substrate 1 at both sides of the gate electrode 2. The dopant regions 19a and 19b act as a source and drain electrode, respectively. An insulation layer 15 is formed on the upper surface of the gate electrode 2, a contact hole is formed on the upper surface of the source electrode 19a and is connected with the bit line 14 and the source electrode 19a, respectively. Another contact hole is formed in a predetermined portion of the drain electrode 19b and is connected with the node electrode 11 and the drain electrode, respectively, of the capacitor. An insulation film 12 which is a dielectric, is formed on the surface of the node electrode 11, and a plate electrode 13 of the capacitor is formed in such a manner that the plate electrode 13 surrounds the dielectric 12.
The conventional fabrication method for a semiconductor device having a fin type capacitor as shown in FIG. 3 will now be explained with reference to FIGS. 4A through 4G.
First, as shown in FIG. 4A, a word line (not shown) is formed on the upper surface of the semiconductor substrate 1, and the gate electrode 2 is connected with the word line. A dopant ion is implanted into the semiconductor substrate 1 at both sides of the gate electrode 2 for thus forming a source electrode 19a and a drain electrode 19b, respectively.
Next, as shown in FIG. 4B, a Si.sub.3 N.sub.4 film 15 which acts as an insulation film, is formed on the semiconductor substrate 1 by a chemical vapor deposition method in such a manner that the Si.sub.3 N.sub.4 film 15 covers the gate electrode 2.
As shown in FIG. 4C, a first silicon oxide film 60, a polysilicon layer 61, and a second silicon oxide film 62 are sequentially formed on the Si.sub.3 N.sub.4 film 15 which acts as an insulation film, and the first silicon oxide film 60, the polysilicon layer 61, and the second silicon oxide film 62 which are formed on the upper surface of the drain electrode 19b are etched for thus forming a contact hole 18 and exposing the drain electrode 19b.
As shown in FIG. 4D, a second polysilicon film 63 is deposited in the contact hole 18 and on the upper surface of the second silicon oxide film 62, respectively, and an n-type dopant is doped thereon in order to reduce the resistance of the second polysilicon film 63.
As shown in FIG. 4E, the second polysilicon film 63 is patterned, and the second silicon oxide film 62 is etched and is fully removed. Thereafter, as shown in FIG. 4F, the first polysilicon film 61 is patterned, and the first silicon oxide film 60 formed below the first polysilicon film 61 is etched and removed for thus forming a node electrode 11 of the capacitor as shown in FIG. 4F.
As shown in FIG. 4G, an insulation film 12 which acts as a dielectric, is formed on the surface of the node electrode 11 of the capacitor, and a polysilicon layer 13 is formed on the surface of the insulation film 12 for thus forming a plate electrode 13 of the capacitor. Thereafter, the insulation film 15 formed on the source electrode 19a is etched, thus forming a contact hole. A polysilicon layer is formed on the upper surface of the insulation film 15 and is patterned, thus forming a bit line 14 and finishing the fabrication of a semiconductor device.
As integration of the semiconductor device is increased, and a space for forming a capacitor therein is reduced, there is a limit for increasing the electrostatic capacity of a conventional capacitor. In addition, in the conventional semiconductor device, as integration is increased, the length of a word line is shortened, and the short channel effect occurs thereby. Furthermore, a contact error may occur in the source and drain electrodes, and a contact resistance may be increased, thus extending an operational time of a cell.